This invention relates to semiconductor memory devices and, more particularly, to a technology effective in utilizing for a Y-system-relief technology on a dynamic RAM (Random Access Memory) of so-called a one-cross-point scheme having dynamic memory cells arranged at cross points between the word lines and the bit lines.
In the research done after completing the present invention, there have been revealed Japanese Patent Laid-open No. 178698/1984 (hereinafter, referred to as Prior Art 1) and Japanese Patent Laid-open No. 20300/1986 (hereinafter, referred to as Prior Art 2) as the dynamic-RAM redundant relief technologies of the open-bit-line type (one-cross-point scheme), hereinafter explained, considered related to the present invention. The publication of Prior Art 1 discloses a 64K-bit dynamic RAM provided with spare arrays. The publication of Prior Art 2 discloses a one-cross-point dynamic type memory provided with a redundant relief circuit. However, there found no conception that a plurality of memory mats are provided in a direction of the bit line to effectively relieve a failed bit line on a mat-by-mat basis as disclosed in the dynamic RAM according to the present invention, hereinafter referred.
Various methods for memory relief are disclosed in the following references, Japanese Patent Laid-Open Nos. 151895/1985, 1511896/1985, 60489/1983, 77946/1986, 151899/1986 and 219597/1999.
The present inventor has noted on the fact that bit-line failures includes the case the failure is on the memory cell itself and the case the failure is on the bit line, and conceived for improving the efficiency of using the redundant bit lines and positively relieving from bit-line failure where memory mats in plurality are provided in the bit-line direction.
It is an object of this invention to provide a semiconductor memory device that realizes effective, rational Y-system relief. Another object of the invention is to provide a semiconductor memory device that is simple in structure but realizes effective Y-system relief. The above and other objects and novel features of the invention will be made apparent from the description of the specification and the accompanying drawings.
The outline of the representative of the inventions as disclosed in the present specification, if briefly explained, is as follows. In a bit-line direction, a plurality of memory mats are arranged including a plurality of memory cells respectively coupled to bit lines and word lines, and further a sense amplifier array is arranged including a plurality of latch circuits having input/output nodes connected to a half of bit-line pairs separately provided to the memory mats in a region between the memory mats placed in the bit-line direction, thereby making possible to replace with a redundant bit-line pair and the corresponding redundant sense amplifier on a basis of each bit-line pair and the sense amplifier connected thereto.